1. Field of the Invention
The invention relates to a delay device for delaying a digital serial input signal SIN by an integer number of M bit periods H, so by a time .tau.=M.H., and for transforming it into a delayed digital serial output signal SOUT having the same bit rate as SIN, the number M being programmable in steps.
The device in accordance with the invention enables delays of some megabits to be obtained with clock frequencies (bit rates) which may exceed 100 MHz. Such a performance enables easy application of this device notably for known error correction code devices which are used in the field of telecommunication, for example for realising delays in excess of 500 bit periods with a bit rate in the order of 40 MHz. Generally speaking, such a device can be used wherever it is necessary to delay a digital signal without changing the rhythm, as is the case in devices of the first-in-first-out type (FIFO). Another use in the telecommunication field is baseband filtering and, in the video field, two-dimensional filtering and other applications stemming from the emergence of digital television.
2. Description of the Related Art
The prior art in this technical field suffers, for example from the technical problem that the horizontal contours of a video image must be extracted by calculation of the gradient of two points situated on the same vertical. This operation necessitates the delay of a video line in order to compare it with the next line; for example, 4 delay devices which each have a capacity of several hundreds of pixels are required for this purpose.
The following solutions are known and used at present in order to solve this kind of problem:
The use of analog delay lines which are also capable of treating digital signals.
These lines are realised by association of active elements such as amplifiers and passive elements such as choke coils and capacitances. They have the drawback that they are asynchronous, that they are not stable in time because of the drift of the passive components, that their programming capacity is limited, and that they are expensive.
The use of CCD (charge-coupled device) delay lines
These lines are formed by a series of cells capable of storing an electric charge, the cells being interconnected by MOS transistors which enable, in the conductive state, the passage of charges from one cell to the next. In a CCD system there can be distinguished a voltage/current converter, the CCD array and its control signals, a current/voltage converter, and an output sampling device. The drawbacks of CCD lines consist in that they are slow (clock frequency less than 20 MHz), that they are difficult to deploy (several supply voltages are necessary), that it is impossible to obtain a programmable delay, and that they are costly.
The use of programmable flip-flop registers (D flip-flops)
The operation of these registers, having characteristics which are close to those envisaged by the invention, is fully digital and they are widely used and easily deployed. The shift frequencies may reach very high values (in excess of 100 MHz) and these registers are readily programmable. A major drawback, however, still resides in the realisation of long delays, given the fact that each delay bit period necessitates the use of a flip-flop with its specific clock input; moreover, the use of numerous switches for creating long delays imposes the problem of excessive propagation times. For long delays, in excess of 500 bit periods, the number of flip-flops required becomes prohibitive and the cost becomes very high. For example, there is known the shift register HEF 4557 B, manufactured by Philips, which is programmable from 1 to 64 bits and which can operate at a clock frequency of 20 MHz. Typically below 15 V, there is also known the shift register AMD 2804 which is manufactured by the United States company AMD and which can produce delays of between 1 and 256 bits at clock frequencies of 4 MHz.